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PRELIMINARY
VTM V*I Chip - VTM Voltage Transformation Module
TM
V048K160T015
K indicates BGA configuration. For other mounting options see Part Numbering below.
* 48 V to 16 V V*I Chip Converter * 15.0 A (22.5 A for 1 ms) * High density - 974 W/in3 * Small footprint - 220 W/in2 * Low weight - 0.5 oz (14 g) * Pick & Place / SMD
* 125C operation * 1 s transient response * 3.5 million hours MTBF * Typical efficiency 96% * No output filtering required * Surface mount BGA or J-Lead packages Vf = 26 - 55 V VOUT = 8.67 - 18.3 V IOUT = 15.0 A K = 1/3 ROUT = 35.0 m max
(c)
Actual size
Product Description
The V048K160T015 V*I Chip Voltage Transformation Module (VTM) excels at speed, density and efficiency to meet the demands of advanced power applications while providing isolation from input to output. It achieves a response time of less than 1 s and delivers up to 15.0 A in a volume of less than 0.25 in3 with unprecedented efficiency. It may be paralleled to deliver higher power levels at an output voltage settable from 8.67 to 18.3 Vdc. The VTM V048K160T015's nominal output voltage is 16 Vdc from a 48 Vdc input Factorized Bus, Vf, and is controllable from 8.67 to 18.3 Vdc at no load, and from 8.15 to 17.9 Vdc at full load, over a Vf input range of 26 to 55 Vdc. It can be operated either open- or closedloop depending on the output regulation needs of the application. Operating open-loop, the output voltage tracks its Vf input voltage with a transformation ratio, K = 1/3 , for applications requiring an isolated output voltage with high efficiency. Closing the loop back to an input Pre-Regulation Module (PRM) or DC-DC converter enables tight load regulation. The 16 V VTM achieves a power density of 974 W/in3 in a V*I Chip package compatible with standard pick-andplace and surface mount assembly processes. The V*I Chip BGA package supports in-board mounting with a low profile of 0.16" (4 mm) over the board. A J-lead package option supports on-board surface mounting with a profile of only 0.25" (6 mm) over the board. The VTM's fast dynamic response and low noise eliminate the need for bulk capacitance at the load, substantially increasing system density while improving reliability and decreasing cost.
Absolute Maximum Ratings
Parameter
+In to -In +In to -In PC to -In VC to -In +Out to -Out Isolation voltage Output current Peak output current Output power Peak output power Case temperature Operating junction temperature (1) Storage temperature
Values
-1.0 to 60.0 100 -0.3 to 7.0 -0.3 to 19.0 -0.1 to 25.0 2,250 15.0 22.5 269 403 208 -40 to 125 -55 to 125 -40 to 150 -65 to 150
Unit
Vdc Vdc Vdc Vdc Vdc Vdc A A W W C C C C C
Notes
For 100 ms
Input to Output Continuous For 1 ms Continuous For 1 ms During reflow T - Grade M - Grade T - Grade M - Grade
Note:
(1) The referenced junction is defined as the semiconductor having the highest temperature. This temperature is monitored by a shutdown comparator.
Part Numbering
V
Voltage Transformation Module
048
Input Voltage Designator
K
160
Output Voltage Designator (=VOUT x10)
T
015
Output Current Designator (=IOUT)
Configuration Options F = On-board (Figure 15) K = In-board (Figure 14)
Product Grade Temperatures (C) Grade Storage Operating T -40 to150 -40 to125 M -65 to150 -55 to125
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V*I Chip Voltage Transformation Module
V048K160T015
Rev. 1.0
Page 1 of 15
PRELIMINARY
Electrical Specifications Input Specs (Conditions are at 48 Vin, full load, and 25C ambient unless otherwise specified)
Parameter
Input voltage range Input dV/dt Input overvoltage turn-on Input overvoltage turn-off Input current Input reflected ripple current No load power dissipation Internal input capacitance Internal input inductance 138 3.1 4.0 20 4.3 55.0 59.5 5.4
V*I Chip Voltage Transformation Module
Min
26
Typ
48
Max
55 1
Unit
Vdc V/s Vdc Vdc Adc mA p-p W F nH
Note
Operable down to zero V with VC voltage applied
Using test circuit in Figure 16; See Figure 1
Output Specs (Conditions are at 48 Vin, full load, and 25C ambient unless otherwise specified)
Parameter
Output voltage Rated DC current Peak repetitive current Short circuit protection set point Current share accuracy Efficiency Half load Full load Internal output inductance Internal output capacitance Output overvoltage setpoint Output ripple voltage No external bypass 10 F bypass capacitor Effective switching frequency Line regulation K Load regulation ROUT Transient response Voltage overshoot Response time Recovery time 15.3 18.2 5 96.0 95.7 1.6 25.4
Min
8.67 8.15 0
Typ
Max
18.3 17.9 15.0 22.5 21.8 10
Unit
Vdc Vdc Adc A Adc % % % nH F Vdc
Note
No load Full load 26 - 55 VIN Max pulse width 1ms, max duty cycle 10%, baseline power 50% Module will shut down See Parallel Operation on Page 10 See Figure 3 See Figure 3 Effective value Module will shut down See Figures 2 and 5 See Figure 6 Fixed, 1.8 MHz per phase VOUT = K*VIN at no load
95.5 95.0
18.3 153 13.4 3.6 1/3 29.7 245 200 1 220 3.7 0.3367 35.0
3.3 0.3300
mV mV MHz
m mV ns s
See Figure 19 15.0 A load step with 100 F CIN; See Figures 7 and 8 See Figures 7 and 8 See Figures 7 and 8
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V*I Chip Voltage Transformation Module
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Page 2 of 15
PRELIMINARY
Electrical Specifications (continued) Waveforms
Ripple vs. Output Current
160
Output Ripple (mVpk-pk)
140 120 100 80 60 40 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15
Output Current (A) Figure 1-- Input reflected ripple current at full load and 48 Vf. Figure 2-- Output voltage ripple vs. output current at 16 Vout with no POL bypass capacitance.
Efficiency vs. Output Current
98 96 Power Dissipation (W) 94
12 11 10 9 8 7 6 5 4 3
Power Dissipation
Efficiency (%)
92 90 88 86 84 82 80 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15
2 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15
Output Current (A) Figure 3-- Efficiency vs. output current at 48 Vf.
Output Current (A)
Figure 4--Power dissipation as a function of output current at 48 Vf.
Figure 5-- Output voltage ripple at full load and 16 Vout; without any external bypass capacitor.
Figure 6--Output voltage ripple at full load and 16 Vout with 10 F ceramic external bypass capacitance and 20 nH distribution inductance.
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V*I Chip Voltage Transformation Module
V048K160T015
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Page 3 of 15
PRELIMINARY
Electrical Specifications (continued)
V*I Chip Voltage Transformation Module
Figure 7-- 0-15.0 A step load change with 47 F input capacitance and no output capacitance.
Figure 8-- 15.0-0 A step load change with 47 F input capacitance and no output capacitance.
General
Parameter
MTBF MIL-HDBK-217F Isolation specifications Voltage Capacitance Resistance Agency approvals (pending) Mechanical parameters Weight Dimensions Length Width Height
Min
Typ
3.5
Max
Unit
Mhrs Vdc pF M
Note
25C, GB Input to Output Input to Output Input to Output UL/CSA 60950, EN 60950 Low voltage directive See Mechanical Drawing, Figures 10 and 12
2,250 3,000 10 cTUVus CE Mark 0.5 / 14.0 1.26 / 32 0.85 / 21.5 0.23 / 5.9
oz / g in / mm in / mm in / mm
Auxiliary Pins (Conditions are at 48 Vin, full load, and 25C ambient unless otherwise specified)
Parameter
Primary Control (PC) DC voltage Module disable voltage Module enable voltage Current limit Disable delay time VTM Control (VC) External boost voltage External boost duration
Min
4.8 2.4 2.4
Typ
5.0 2.5 2.5 2.5 10 14.0 10
Max
5.2 2.6 2.9
Unit
Vdc Vdc Vdc mA s Vdc ms
Note
VC voltage must be applied when module is enabled using PC Source only PC low to Vout low Required for VTM start up without PRM Vin > 26 Vdc. VC must be applied continuously if Vin < 26 Vdc.
12.0
19.0
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V*I Chip Voltage Transformation Module
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Page 4 of 15
PRELIMINARY
Electrical Specifications (continued) Thermal
Symbol Parameter
Over temperature shutdown Thermal capacity Junction-to-case thermal impedance Junction-to-BGA thermal impedance Junction-to-ambient (1) Junction-to-ambient (2)
Min
125
Typ
130 0.61 1.1 2.1 6.5 5.0
Max
135
Unit
C Ws/C C/W C/W C/W C/W
Note
Junction temperature
RJC RJB RJA RJA Notes:
(1) V048K160T015 surface mounted in-board to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM. (2) V048K160T015 with a 0.25"H heatsink surface mounted on FR4 board, 300 LFM.
V*I Chip Stress Driven Product Qualification Process
Test
High Temperature Operational Life (HTOL) Temperature cycling High temperature storage Moisture resistance Temperature Humidity Bias Testing (THB) Pressure cooker testing (Autoclave) Highly Accelerated Stress Testing (HAST) Solvent resistance/marking permanency Mechanical vibration Mechanical shock Electro static discharge testing - human body model Electro static discharge testing - machine model Highly Accelerated Life Testing (HALT) Dynamic cycling Note: (1) For details of the test protocols see Vicor's website.
Standard
JESD22-A-108-B JESD22-A-104B JESD22-A-103A JESD22-A113-B EIA/JESD22-A-101-B JESD22-A-102-C JESD22-A-110B JESD22-B-107-A JESD22-B-103-A JESD22-B-104-A EIA/JESD22-A114-A EIA/JESD22-A115-A Per Vicor Internal Test Specification(1) Per Vicor internal test specification(1)
Environment
125C, Vmax, 1,008 hrs -55C to 125C, 1,000 cycles 150C, 1,000 hrs Moisture sensitivity Level 5 85C, 85% RH, Vmax, 1,008 hrs 121C, 100% RH, 15 PSIG, 96 hrs 130C, 85% RH, Vmax, 96 hrs Solvents A, B & C as defined 20g peak, 20-2,000 Hz, test in X, Y & Z directions 1,500g peak 0.5 ms pulse duration, 5 pulses in 6 directions Meets or exceeds 2,000 Volts Meets or exceeds 200 Volts Operation limits verified, destruct margin determined Constant line, 0-100% load, -20C to 125C
V*I Chip Ball Grid Array Interconnect Qualification
Test
BGA solder fatigue evaluation Solder ball shear test
Standard
IPC-9701 IPC-SM-785 IPC-9701
Environment
Cycle condition: TC3 (-40 to +125C) Test duration: NTC-B (500 failure free cycles) Failure through bulk solder or copper pad lift-off
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V*I Chip Voltage Transformation Module
V048K160T015
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Page 5 of 15
PRELIMINARY
Pin/Control Functions
+IN/-IN DC Voltage Ports The VTM input should not exceed the maximum specified. Be aware of this limit in applications where the VTM is being driven above its nominal output voltage. If less than 26 Vdc is present at the +In and -In ports, a continuous VC voltage must be applied for the VTM to process power. Otherwise VC voltage need only be applied for 10 ms after the voltage at the +In and -In ports has reached or exceeded 26 Vdc. If the input voltage exceeds the overvoltage turn-off, the VTM will shutdown. The VTM does not have internal input reverse polarity protection. Adding a properly sized diode in series with the positive input or a fused reverse-shunt diode will provide reverse polarity protection. TM - For Factory Use Only
-Out
V*I Chip Voltage Transformation Module
43 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
21 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
+Out
+In
-Out
TM VC PC
+Out
-In
VC - VTM Control The VC port is multiplexed. It receives the initial VCC voltage from an upstream PRM, synchronizing the output rise of the VTM with the output rise of the PRM. Additionally, the VC port provides feedback to the PRM to compensate for the VTM output resistance. In typical applications using VTMs powered from PRMs, the PRM's VC port should be connected to the VTM VC port. In applications where a VTM is being used without a PRM, 14 V must be supplied to the VC port for as long as the input voltage is below 26 V and for 10 ms after the input voltage has reached or exceeded 26 V. The VTM is not designed for extended operation below 26 V. The VC port should only be used to provide VCC voltage to the VTM during startup. PC - Primary Control
Figure 9--VTM BGA configuration
Bottom View
Signal Name +In -In TM VC PC +Out -Out
BGA Designation A1-L1, A2-L2 AA1-AL1, AA2-AL2 P1, P2 T1, T2 V1, V2 A3-G3, A4-G4, U3-AC3, U4-AC4 J3-R3, J4-R4, AE3-AL3, AE4-AL4
The Primary Control (PC) port is a multifunction port for controlling the VTM as follows: Disable - If PC is left floating, the VTM output is enabled. To disable the output, the PC port must be pulled lower than 2.4 V, referenced to -In. Optocouplers, open collector transistors or relays can be used to control the PC port. Once disabled, 14 V must be re-applied to the VC port to restart the VTM. Primary Auxiliary Supply - The PC port can source up to 2.4 mA at 5 Vdc. +OUT/-OUT DC Voltage Output Ports The output and output return are through two sets of contact locations. The respective +Out and -Out groups must be connected in parallel with as low an interconnect resistance as possible. Within the specified input voltage range, the Level 1 DC behavioral model shown in Figure 19 defines the output voltage of the VTM. The current source capability of the VTM is shown in the specification table. To take full advantage of the VTM, the user should note the low output impedance of the device. The low output impedance provides fast transient response without the need for bulk POL capacitance. Limitedlife electrolytic capacitors required with conventional converters can be reduced or even eliminated, saving cost and valuable board real estate.
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V*I Chip Voltage Transformation Module
V048K160T015
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Page 6 of 15
PRELIMINARY
Mechanical Drawings
1,00 0.039
SOLDER BALL #A1 INDICATOR
18,00 0.709 9,00 0.354
1,00 0.039
SOLDER BALL #A1
21,5 0.85
5,9 0.23
(106) X O 0.020 SOLDER BALL 0.51
1,00 TYP 0.039
OUTPUT
30,00 1.181
INPUT
INPUT
OUTPUT
32,0 1.26
28,8 1.13 16,0 0.63
C L
15,00 0.591
TOP VIEW (COMPONENT SIDE)
1,6 0.06
C L
BOTTOM VIEW
1,00 0.039
3,9 0.15 NOTES: mm 1- DIMENSIONS ARE inch . 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005] 3- PRODUCT MARKING ON TOP SURFACE
15,6 0.62
SEATING PLANE
Figure 10-- V T M BGA mechanical outline; Inboard mounting
IN-BOARD MOUNTING BGA surface mounting requires a cutout in the PCB in which to recess the V*I Chip
0,51 ) 0.020 0,50 0.020
1,50 0.059 ( 1,00 ) 0.039 (o o 0,53 PLATED VIA 0.021
CONNECT TO INNER LAYERS
SOLDER MASK DEFINED PADS
0,50 0.020
( 1,00 ) 0.039 1,00 0.039 9,00 0.354
1
18,00 0.709
1,00 0.039
1,00 0.039
SOLDER PAD #A1
(2) X 10,00 0.394
+IN
(4) X 6,00 0.236
+OUT1 -OUT1
RECOMMENDED LAND AND VIA PATTERN
TM
(COMPONENT SIDE SHOWN)
PCB CUTOUT
VC
29,26 1.152 24,00 0.945 16,00 0.630 8,00 0.315 0,37 0.015 1,6 (4) X R 0.06 NOTES: mm 1- DIMENSIONS ARE inch . 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
20,00 0.787 17,00 0.669 15,00 13,00 0.591 0.512
+OUT2
-IN
PC
31
-OUT2
(106) X o
0,51 0.020
8,08 0.318 16,16 0.636
SOLDER MASK DEFINED PAD
Figure 11-- VTM BGA PCB land/VIA layout information; Inboard mounting
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V*I Chip Voltage Transformation Module
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Page 7 of 15
PRELIMINARY
Mechanical Drawings (continued)
V*I Chip Voltage Transformation Module
22,0 0.87
6,1 0.24
3,01 0.118
15,99 0.630
3,01 0.118
(4) PL. 7,10 0.280 OUTPUT INPUT
11,10 (2) PL. 0.437
32,0 1.26
INPUT
24,00 0.945 16,00 0.630
TOP VIEW (COMPONENT SIDE)
Figure 12-- V T M J-Lead mechanical outline; Onboard mounting
(4) X 11,48 0.452
(6) X
1,60 0.063
+IN
20,00 (2) X 0.787 (2) X16,94 0.667 (2) X14,94 0.588 12,94 (2) X 0.509
PC VC TM
-IN
Figure 13-- VTM J-Lead PCB land layout information; Onboard mounting
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OUTPUT NOTES: 1- DIMENSIONS ARE mm/[INCH]. 3,26 0.128 1,38 0.054 TYP 15,74 0.620
C L
15,55 0.612 8,00 0.315
C L
12,94 0.509
14,94 0.588
16,94 0.667
20,00 0.787
0,45 0.018
BOTTOM VIEW
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005] 3- PRODUCT MARKING ON TOP SURFACE
3,26 0.128 0,51 TYP 0.020
RECOMMENDED LAND PATTERN
(COMPONENT SIDE SHOWN)
+OUT1 -OUT1 +OUT2 -OUT2 8,00 (2) X 0.315 (2) X 16,00 0.630
7,48 (8) X 0.295
(2) X 24,00 0.945
NOTES: 1- DIMENSIONS ARE mm/[INCH]. 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
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V*I Chip Voltage Transformation Module
V048K160T015
Rev. 1.0
Page 8 of 15
PRELIMINARY
Configuration Options
Configuration Effective power density Junction-Board thermal resistance Junction-Case thermal resistance Junction-Ambient thermal resistance 300LFM
Inboard(1) (Figure 14) 1400 W/in3 2.1 C/W 1.1 C/W 6.5 C/W
Onboard(1) (Figure 15) 880 W/in3 2.4 C/W 1.1 C/W 6.8 C/W
Inboard with 0.25" Heatsink 550 W/in3 2.1 C/W N/A 5.0 C/W
Onboard with 0.25" Heatsink 440 W/in3 2.4 C/W N/A 5.0 C/W
Notes: (1) Surface mounted to a 2" x 2" FR4 board, 4 layers 2 oz Cu
21.5 0.85
22.0 0.87
32.0 1.26
32.0 1.26
4.0 0.16
6.3 0.25
INBOARD MOUNT (V*I Chip recessed into PCB)
mm in
ONBOARD MOUNT
mm in
Figure 14--Inboard mounting - package K
Figure 15--Onboard mounting - package F
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V*I Chip Voltage Transformation Module
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Rev. 1.0
Page 9 of 15
PRELIMINARY
CONFIGURATION OPTIONS (continued)
V*I Chip Voltage Transformation Module
Input reflected ripple measurement point F1 7A Fuse
+In +Out
+ R3 10 m Load C3 10 F - Notes: C3 should be placed close to the load R3 may be ESR of C3 or a seperate damping resistor.
-Out
C1 47 F Al electrolytic
C2 0.47 F ceramic
TM VC PC
VTM
+Out
14 V + -
-In
K Ro
-Out
Figure 16--VTM test circuit
Application Note
Parallel Operation In applications requiring higher current or redundancy, VTMs can be operated in parallel without adding control circuitry or signal lines. To maximize current sharing accuracy, it is imperative that the source and load impedance on each VTM in a parallel array be equal. If VTMs are being fed by an upstream PRM, the VC nodes of all VTMs must be connected to the PRM VC. To achieve matched impedances, dedicated power planes within the PC board should be used for the output and output return paths to the array of paralleled VTMs. This technique is preferable to using traces of varying size and length. The VTM power train and control architecture allow bi-directional power transfer when the VTM is operating within its specified ranges. Bi-directional power processing improves transient response in the event of an output load dump. The VTM may operate in reverse, returning output power back to the input source. It does so efficiently. Thermal Management The high efficiency of the VTM results in low power dissipation minimizing temperature rise, even at full output current. The heat generated within the internal semiconductor junctions is coupled through very low thermal resistances, RJC and RJB (see Figure 17), to the PC board allowing flexible thermal management. CASE 1 Convection via optional Heat Sink to air. In an environment with forced convection over the surface of a PCB with 0.4" of headroom, a VTM with a 0.25" heat sink offers a simple thermal management option. The total Junction to Ambient thermal resistance of a surface mounted V048K160T015 with a heat sink attached is 4.8 C/W in 300 LFM airflow, (see Figure 18). At 16 Vout and full rated current (15.0A), the VTM dissipates approximately 11 W per Figure 4. This results in a temperature rise of approximately 53 C, allowing operation in an air temperature of 72 C without exceeding the 125 C max junction temperature. CASE 2 Conduction via the PC board to air The low Junction to BGA thermal resistance allows the use of the PC board as a means of removing heat from the VTM. Convection from the PC board to ambient, or conduction to a cold plate, enable flexible thermal management options. With a VTM mounted on a 2.0 in2 area of a multi-layer PC board with appropriate power planes resulting in 8 oz of effective copper weight, the Junction-to-BGA thermal resistance, RJA, is 6.5 C/W in 300 LFM of air. With a maximum junction temperature of 125 C and 11 W of dissipation at full current of 15.0 A, the resulting temperature rise of 72 C allows the VTM to operate at full rated current up to a 53 C ambient temperature. See thermal resistances on Page 9 for additional details on this thermal management option. Adding low-profile heat sinks to the PC board can lower the thermal resistance of the PC board surrounding the VTM. Additional cooling may be added by coupling a cold plate to the PC board with low thermal resistance stand offs. CASE 3 Combined direct convection to the air and conduction to the PC board. A combination of cooling techniques that utilize the power planes and dissipation to the air will also reduce the total thermal impedance. This is the most effective cooling method. To estimate the total effect of the combination, treat each cooling branch as one leg of a parallel resistor network.
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V*I Chip Voltage Transformation Module
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Rev. 1.0
Page 10 of 15
PRELIMINARY
Application Note (continued)
VTM with 0.25'' heat sink
10 9 8
Tja
7 6 5 4 3 0 100 200 300 400 500 600
Airflow (LFM)
Figure 17--Thermal resistance
Figure 18--Junction-to-ambient thermal resistance of VTM with 0.25" Heat Sink.
V*I Chip VTM Level 1 DC Behavioral Model for 48 V to 16 V, 15.0 A
IOUT ROUT
29.7 m 1/3 * Iout
+
V*I
1/3 * Vin
+
VIN
IQ
65 mA
+ -
K
+
VOUT
-
-
(c)
-
Figure 19--This model characterizes the DC operation of the V*I Chip VTM, including the converter transfer function and its losses. The model enables estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.
V*I Chip VTM Level 2 Transient Behavioral Model for 48 V to 16 V, 15.0 A
1.8 nH
LIN = 20 nH LIN = 20 nH
IOUT
ROUT
29.7 m
LOUT = 1.6 nH
+
CIN VIN
RCIN RCIN
1.3 m 1/3 * Iout 4.0 F
V*I
6.9 m
RCOUT RCOUT
+
0.21 m 25.4 F
IQ
65 mA
+ -
K
+ -
1/3 * Vin
COUT
VOUT
-
-
(c)
Figure 20--This model characterizes the AC operation of the V*I Chip VTM including response to output load or input voltage transients or steady state modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load with or without external filtering elements.
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V*I Chip Voltage Transformation Module
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Rev. 1.0
Page 11 of 15
PRELIMINARY
Application Note (continued)
In Figures 21 - 23; K = VTM Transformation Ratio RO = VTM Output Resistance V*I Chip Voltage Transformation Module
Vf = PRM Output (Factorized Bus Voltage) VO = VTM Output VL = Desired Load Voltage
FPA Adaptive Loop
Vo = VL 1.0%
VC PC TM IL NC PR VH SC SG OS NC CD
ROS RCD
PRM-AL
+In +Out
Factorized Bus (Vf)
Vf = VL (Io*Ro) + K K
+In
+Out
-Out TM VC PC
VTM
+Out
Vin
-In -Out
-In
K Ro
L O A D
-Out
Figure 21 -- The PRM controls the factorized bus voltage, Vf, in proportion to output current to compensate for the output resistance, Ro, of the VTM. The VTM output voltage is typically within 1% of the desired load voltage (VL) over all line and load conditions.
FPA Non-isolated Remote Loop
Remote Loop Control
VC PC TM IL NC PR VH SC SG OS NC CD
Vo = VL 0.4%
PRM-AL
+In +Out
Factorized Power Bus
Vf = f (Vs)
+In
+Out
+S
-Out TM VC PC
VTM
+Out
Vin
-In -Out
-In
K Ro
-S
-Out
L O A D
Figure 22 -- An external error amplifier or Point-of-Load IC (POLIC) senses the load voltage and controls the PRM output - the Factorized Bus - as a function of output current, compensating for the output resistance of the VTM and for distribution resistance.
FPA Isolated Remote Loop
Remote Loop Control
Vo = VL 0.4%
VC PC TM IL NC PR +In VS FB FG NC NC NC +In +Out
PRM-IF
Factorized Power Bus
Vf = f (Vs)
+S
-Out TM VC PC
+Out
VTM
+Out
Vin
-In -Out
-In
K Ro
-S
-Out
L O A D
Figure 23--An external error amplifier or Point-of-Load IC (POLIC) senses the load voltage and controls the PRM output - the factorized bus - as a function of output current, compensating for the output resistance of the VTM and for distribution resistance. The Factorized Bus voltage (Vf) increases in proportion to load current. The remote feedback loop is isolated within the PRM to support galvanic isolation and hipot compliance at the system level.
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V*I Chip Voltage Transformation Module
V048K160T015
Rev. 1.0
Page 12 of 15
PRELIMINARY
Application Note (continued)
V*I Chip soldering recommendations V*I Chip modules are intended for reflow soldering processes. The following information defines the processing conditions required for successful attachment of a V*I Chip to a PCB. Failure to follow the recommendations provided can result in aesthetic or functional failure of the module. Storage V*I Chip modules are currently rated at MSL 5. Exposure to ambient conditions for more than 72 hours requires a 24 hour bake at 125C to remove moisture from the package. Solder paste stencil design Solder paste is recommended for a number of reasons, including overcoming minor solder sphere co-planarity issues as well as simpler integration into overall SMD process. 63/37 SnPb, either no-clean or water-washable, solder paste should be used. Pb-free development is underway. The recommended stencil thickness is 6 mils. The apertures should be 20 mils in diameter for the Inboard (BGA) application and 0.9-0.9:1 for the Onboard (J-Leaded). Pick and place Inboard (BGA) modules should be placed as accurately as possible to minimize any skewing of the solder joint; a maximum offset of 10 mils is allowable. Onboard (J-Leaded) modules should be placed within 5 mils. To maintain placement position, the modules should not be subjected to acceleration greater than 500 in/sec2 prior to reflow. Reflow There are two temperatures critical to the reflow process; the solder joint temperature and the module's case temperature. The solder joint's temperature should reach at least 220C, with a time above liquidus (183C) of ~30 seconds. The module's case temperature must not exceed 208 C at anytime during reflow. Because of the T needed between the pin and the case, a forced-air convection oven is preferred for reflow soldering. This reflow method generally transfers heat from the PCB to the solder joint. The module's large mass also reduces its temperature rise. Care should be taken to prevent smaller devices from excessive temperatures. Reflow of modules onto a PCB using Air-Vac-type equipment is not recommended due to the high temperature the module will experience.
Figure 25-- Properly reflowed V*I Chip J-Lead
16 Soldering Time
Removal and rework V*I Chip modules can be removed from PCBs using special tools such as those made by Air-Vac. These tools heat a very localized region of the board with a hot gas while applying a tensile force to the component (using vacuum). Prior to component heating and removal, the entire board should be heated to 80-100C to decrease the component heating time as well as local PCB warping. If there are adjacent moisture-sensitive components, a 125C bake should be used prior to component removal to prevent popcorning. V*I Chip modules should not be expected to survive a removal operation.
239
Joint Temperature, 220C Case Temperature, 208C
183 165
degC
91
Figure 24--Thermal profile diagram
Inspection For the BGA-version, a visual examination of the post-reflow solder joints should show relatively columnar solder joints with no bridges. An inspection using x-ray equipment can be done, but the module's materials may make imaging difficult. The J-Lead versions solder joints should conform to IPC 12.2 * Properly wetted fillet must be evident. * Heel fillet height must exceed lead thickness plus solder thickness.
vicorpower.com
800-735-6200
V*I Chip Voltage Transformation Module
V048K160T015
Rev. 1.0
Page 13 of 15
PRELIMINARY
Application Note (continued)
Input Impedance Recommendations To take full advantage of the VTM's capabilities, the impedance of the source (input source plus the PC board impedance) must be low over a range from DC to 5 MHz. The input of the VTM (factorized bus) should be locally bypassed with a 8 F low Q aluminum electrolytic capacitor. Additional input capacitance may be added to improve transient performance or compensate for high source impedance. The VTM has extremely wide bandwidth so the source response to transients is usually the limiting factor in overall output response of the VTM. Anomalies in the response of the source will appear at the output of the VTM, multiplied by its K factor of 1/3 . The DC resistance of the source should be kept as low as possible to minimize voltage deviations on the input to the VTM. If the VTM is going to be operating close to the high limit of its input range, make sure input voltage deviations will not trigger the input overvoltage turn-off threshold. V*I Chip Voltage Transformation Module Input Fuse Recommendations V*I Chips are not internally fused in order to provide flexibility in configuring power systems. However, input line fusing of V*I Chips must always be incorporated within the power system. A fast acting fuse is required to meet safety agency Conditions of Acceptability. The input line fuse should be placed in series with the +In port.
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages.
vicorpower.com
800-735-6200
V*I Chip Voltage Transformation Module
V048K160T015
Rev. 1.0
Page 14 of 15
Vicor's comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor's Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department.
Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Vicor Express: vicorexp@vicr.com Technical Support: apps@vicr.com
vicorpower.com
800-735-6200
V*I Chip Voltage Transformation Module
V048K160T015
Rev. 1.0
4/05

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